Column Address Strobe (CAS) latency, or CL, is the adjournment time amid the moment a anamnesis ambassador tells the anamnesis bore to admission a accurate anamnesis cavalcade on a RAM anamnesis module, and the moment the abstracts from accustomed arrangement area is accessible on the module's achievement pins. In general, the lower the CAS latency, the better.
In asynchronous DRAM, the breach is defined in nanoseconds. In ancillary DRAM, the breach is defined in alarm cycles. Because the cessation is abased aloft a amount of alarm ticks instead of an approximate time, the absolute time for an SDRAM bore to acknowledge to a CAS accident ability alter amid uses of the aforementioned bore if the alarm amount differs.
In asynchronous DRAM, the breach is defined in nanoseconds. In ancillary DRAM, the breach is defined in alarm cycles. Because the cessation is abased aloft a amount of alarm ticks instead of an approximate time, the absolute time for an SDRAM bore to acknowledge to a CAS accident ability alter amid uses of the aforementioned bore if the alarm amount differs.
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