CAS latency

Column Address Strobe (CAS) latency, or CL, is the adjournment time amid the moment a anamnesis ambassador tells the anamnesis bore to admission a accurate anamnesis cavalcade on a RAM anamnesis module, and the moment the abstracts from accustomed arrangement area is accessible on the module's achievement pins. In general, the lower the CAS latency, the better.

In asynchronous DRAM, the breach is defined in nanoseconds. In ancillary DRAM, the breach is defined in alarm cycles. Because the cessation is abased aloft a amount of alarm ticks instead of an approximate time, the absolute time for an SDRAM bore to acknowledge to a CAS accident ability alter amid uses of the aforementioned bore if the alarm amount differs.

RAM operation background

Dynamic RAM is abiding in a ellipsoidal array. Anniversary row is called by a accumbent chat line. Sending a analytic top arresting forth a accustomed row enables the MOSFETs present in that row, abutting anniversary accumulator capacitor to its agnate vertical bit line. Anniversary bit band is affiliated to a faculty amplifier which amplifies the baby voltage change produced by the accumulator capacitor. This amplified arresting is again achievement from the DRAM dent as able-bodied as apprenticed aback up the bit band to brace the row.

When no chat band is active, the arrangement is abandoned and the bit curve are captivated in a precharged state, with a voltage center amid top and low. This general arresting is deflected appear top or low by the accumulator capacitor if a row is fabricated active.

To admission memory, a row have to aboriginal be called and loaded into the faculty amplifiers. This row is again alive and columns may be accessed for apprehend or write.

The CAS cessation is the adjournment amid the time at which the cavalcade abode and the cavalcade abode strobe arresting are presented to the anamnesis bore and the time at which the agnate abstracts is fabricated accessible by the anamnesis module. The adapted row have to already be active; if it is not, added time is required.

As an example, a archetypal 1 GiB SDRAM anamnesis bore ability accommodate eight abstracted one-gibibit DRAM chips, anniversary alms 128 MiB of accumulator space. Anniversary dent is disconnected internally into eight banks of 227=128 Mibits, anniversary of which comprises a abstracted DRAM array. Anniversary arrangement contains 214=16384 rows of 213=8192 $.25 each. One byte of anamnesis (from anniversary chip; 64 $.25 absolute from the accomplished DIMM) is accessed by bartering a 3-bit coffer number, a 14-bit row address, and a 10-bit cavalcade address.

Effect on memory access speed

With asynchronous DRAM, the time adjournment amid presenting a cavalcade abode and accepting the abstracts on the achievement pins is constant. Synchronous DRAM, however, has a CAS cessation which is abased aloft the alarm rate. Accordingly, the CAS cessation of an SDRAM anamnesis bore is defined in alarm ticks instead of absolute time.

Because anamnesis modules accept assorted centralized banks, and abstracts can be achievement from one during admission cessation for another, the achievement pins can be kept 100% active behindhand of the CAS cessation through pipelining; the best accessible bandwidth is bent abandoned by the alarm speed. Unfortunately, this best bandwidth can abandoned be accomplished if the abstracts to be apprehend is accepted continued abundant in advance; if the abstracts getting accessed is not predictable, activity stalls can occur, consistent in a accident of bandwidth. For a absolutely alien anamnesis access, the accordant cessation is the time to abutting any accessible row, additional the time to accessible the adapted row, followed by the CAS cessation to apprehend abstracts from it. Due to spatial locality, however, it is accepted to admission several words in the aforementioned row. In this case, the CAS cessation abandoned determines the delayed time.

In general, the lower the CAS latency, the better. Because avant-garde DRAM modules' CAS latencies are defined in alarm ticks instead of time, if comparing latencies at altered alarm speeds, latencies accept to be translated into absolute times to accomplish a fair comparison; a college after CAS cessation may still be a beneath real-time cessation if the alarm is faster. However, it is important to agenda that the manufacturer-specified CAS cessation about assumes the defined alarm rate, so underclocking a anamnesis bore may aswell acquiesce for a lower CAS cessation to be set.

Double abstracts amount RAM operates application two transfers per alarm cycle. The alteration amount is about quoted by manufacturers, instead of the alarm rate, which is bisected of the alteration amount for DDR modules. Because the CAS cessation is defined in alarm cycles, and not alteration ticks (which action on both the absolute and abrogating bend of the clock), it is important to ensure it is the alarm amount which is getting acclimated to compute CAS cessation times, and not the angled alteration rate.

Another complicating agency is the use of access transfers. A avant-garde chip ability accept a accumulation band admeasurement of 64 bytes, acute eight transfers from a 64-bit-wide (8 bytes) anamnesis to fill. The CAS cessation can abandoned accurately admeasurement the time to alteration the aboriginal chat of memory; the time to alteration all eight words depends on the abstracts alteration amount as well. Fortunately, the processor about does not charge to delay for all eight words; the access is usually beatific in analytical chat aboriginal order, and the aboriginal analytical chat can be acclimated by the chip immediately.

In the table below, abstracts ante are accustomed in actor transfers—also accepted as Megatransfers—per additional (MT/s), while alarm ante are accustomed in MHz, actor cycles per second.

Memory timing examples

Memory timing examples (CAS cessation only) Generation Type Data amount Bit time Command amount Cycle time CL First chat Fourth chat Eighth word

SDRAM PC100 100 MT/s  10 ns 100 MHz  10 ns 2 20 ns 50 ns 90 ns

PC133 133 MT/s  7.5 ns 133 MHz  7.5 ns 3 22.5 ns 45 ns 75 ns

DDR SDRAM DDR-333 333 MT/s  3 ns 166 MHz  6 ns 2.5 15 ns 24 ns 36 ns

DDR-400 400 MT/s  2.5 ns 200 MHz  5 ns 3 15 ns 22.5 ns 32.5 ns

2.5 12.5 ns 20 ns 30 ns

2 10 ns 17.5 ns 27.5 ns

DDR2 SDRAM DDR2-667 667 MT/s 1.5 ns 333 MHz  3 ns 5 15 ns 19.5 ns 25.5 ns

4 12 ns 16.5 ns 22.5 ns

DDR2-800 800 MT/s  1.25 ns 400 MHz  2.5 ns 6 15 ns 18.75 ns 23.75 ns

5 12.5 ns 16.25 ns 21.25 ns

4.5 11.25 ns 15 ns 20 ns

4 10 ns 13.75 ns 18.75 ns

DDR2-1066 1066 MT/s  0.95 ns 533 MHz  1.9 ns 7 13.13 ns 15.94 ns 19.69 ns

6 11.25 ns 14.06 ns 17.81 ns

5 9.38 ns 12.19 ns 15.94 ns

4.5 8.44 ns 11.25 ns 15 ns

4 7.5 ns 10.31 ns 14.06 ns

DDR3 SDRAM DDR3-1066 1066 MT/s  0.9375 ns 533 MHz  1.875 ns 7 13.13 ns 15.95 ns 19.7 ns

DDR3-1333 1333 MT/s  0.75 ns 666 MHz  1.5 ns 9 13.5 ns 15.75 ns 18.75 ns

6  9 ns 11.25 ns 14.25 ns

DDR3-1375 1375 MT/s  0.73 ns 687 MHz  1.5 ns 5  7.27 ns  9.45 ns 12.36 ns

DDR3-1600 1600 MT/s  0.625 ns 800 MHz  1.25 ns 9 11.25 ns 13.125 ns 15.625 ns

8 10 ns 11.875 ns 14.375 ns

7  8.75 ns 10.625 ns 13.125 ns

6  7.50 ns 9.375 ns 11.875 ns

DDR3-2000 2000 MT/s  0.5 ns 1000 MHz  1 ns 10 10 ns 11.5 ns 13.5 ns

9 9 ns 10.5 ns 12.5 ns

8  8 ns 9.5 ns 11.5 ns

7  7 ns 8.5 ns 10.5 ns